As critical dimensions of devices in integrated circuits shrink to the limits of common memory cell technologies, designers have been looking to techniques for stacking multiple planes of memory cells to achieve greater storage capacity, and to achieve lower costs per bit.
A structure that provides vertical NAND cells in a charge trapping memory technology is described in Tanaka et al., “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory”, 2007 Symposium on VLSI Technology Digest of Technical Papers; 12-14 Jun. 2007, pages: 14-15. The structure described in Tanaka et al. includes a multi-gate field effect transistor structure having a vertical channel which operates like a NAND gate, using silicon-oxide-nitride-oxide-silicon SONOS charge trapping technology to create a storage site at each gate/vertical channel interface. The memory structure is based on a pillar of semiconductor material arranged as the vertical channel for the multi-gate cell, with a lower select gate adjacent the substrate, and an upper select gate on top. A plurality of horizontal control gates is formed using planar electrode layers that intersect with the pillars. The planar electrode layers used for the control gates do not require critical lithography, and thereby save costs.
The drawback of the 3-D memory structure of the prior art is that the read throughput is reduced because of the need to shield the adjacent bit line coupling effect. An odd-even architecture is proposed for the 3-D memory structure for the adjacent bit line coupling effect. In each read, either even or odd global bit lines are read. The adjacent global bit lines serve a shielding purpose. In this kind of the memory structure, only one-second of the bit lines is accessed in one read operation.
In the odd-even architecture, separate sensing between even and odd bit lines is widely used to avoid bit line to bit line (BL-BL) coupling noise during sensing. When either of even bit lines or odd bit lines is read, the other bit lines are fixed at ground to shield from BL-BL coupling noise. Although separate sensing between even and odd bit lines is more reliable and is easier to design than all BL simultaneous sensing, read time is much longer.